The MSB is complemented for sign extension by generating p ρ, m ¯ in the M LUT5 and p ρ, m in the the M LUT5. This is done for all of the partial-product bits except the MSB, p ρ, m. O5 generates p ρ, i and is selected to drive g e n i. O6 then generates x ρ - 1, i + 2 ⊕ p ρ, i and drives p r o p i. The M LUT5 is configured to generate p ρ, i, and the M LUT5 is configured to generate p ρ, i ¯. x ρ - 1, i + 2 is connected to I6 of the same LUT6. The inputs for each bit, p ρ, i, are connected to the I5:I1 inputs of a LUT6. The carry into the proposed adder, c 0, can be used to implement subtraction or to add an extra bit to the least significant column. Input I6 has the shortest delay path, and I1 has the longest, so this method also allows faster inputs to be used if y i is a function of less than five variables. This frees the bypass input to be connected to the bypass flip-flop to implement additional registers. Figure 6 shows the connections for this configuration. This can be used to add x i and y i without using the bypass input when x i is a function of one variable and y i is a function of up to five variables. If y i ¯ is stored in M, then x i ⊕ y i is generated at O6 and y i is generated at O5. If x i is “1”, the function stored in M is output at O6. The function y i is stored in M, so y i is output at O5. Suppose x i is a function of one variable connected to I6 and y i is a function of five variables connected to I5:I1. However, there are several useful cases where one function of six variables can be output at O6 and a separate function of five shared variables can be output at O5. Normally, a LUT6 can be used to either generate a function of six inputs at O6 or to generate two functions of five inputs at O5 and O6. Kumm and Zipf present two novel GPCs, (6,0,6 5) and (1,3,2,5 5), that are specific to and optimized for Xilinx FPGAs. presents incremental improvements or additional applications for GPCs. Other work on GPCs that is based on work by Parandeh-Afshar et al. They note that both Altera and Xilinx have efficient ternary adders, so they use GPCs to reduce the matrix to three rows. They use a heuristic to implement multi-operand adder compressor trees with GPCs in, use integer linear programming (ILP) to improve the results in and improve the GPCs themselves by using the ALM fast addition resources in. Therefore, they focus on GPCs that have up to six total inputs for efficient usage of the LUTs and show that (6 3), (1,5 3), (2,3 3) and (3,3 4) counters each map to two ALMs in modern Altera FPGAs. They note that modern FPGAs, such as Altera Stratix II and newer and Xilinx Virtex-5 and newer, have 6-input LUTs. are believed to be the first to look at using GPCs implemented using LUTs to build compressor trees for multi-operand addition in FPGAs. use a method similar to this work to implement softcore multipliers. Mhaidat and Hamzah compare the use of GPCs to Wallace and Dadda multipliers. Kumm and Zipf present novel GPCs for Xilinx FPGAs and use them with integer linear programming (ILP) in compressor trees. model a generalized weighted sum of bits as a bit heap and describe techniques for summing them using a combination of embedded multipliers and GPCs on Altera and Xilinx FPGAs. present a method for implementing large multipliers that combine embedded multipliers with GPCs. De Dinechin and Pasca present methods for implementing large multipliers and squarers on Xilinx FPGAs using a combination of embedded multipliers and logic-based multipliers. have also published work on using GPCs for multi-operand addition. suggest modifications to the FPGA logic fabric to improve soft multiplier implementations. using GPCs for compressor trees for the more general case of multi-operand addition. This builds on the previous work of Parandeh-Afshar et al. They present radix-2 Baugh–Wooley multipliers and radix-4-modified Booth multipliers that use generalized parallel counters (GPCs) in the logic fabric to reduce the partial-product matrix to two or three rows, which are then added using a carry-propagate adder (CPA). Parandeh-Afshar and Ienne discuss the importance of this topic and present techniques to improve the performance of soft multipliers in Altera FPGAs.
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